1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a more accurate method for forming an ultra-small gate conductor of an MOS transistor.
2. Description of the Related Art
Fabrication of a metal-oxide semiconductor ("MOS") transistor is well known. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas on the semiconductor substrate by various isolation structures formed upon and within the substrate. Isolation structures come in many forms. For example, the isolation structures can be formed by etching trenches into the substrate and then filling the trenches with a dielectric fill material. Isolation structures may also be formed by locally oxidizing the silicon substrate using the well recognized LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in, for example, an oxidation furnace or a rapid thermal annealer ("RTA"). A gate conductor material is then deposited across the entire dielectric-covered substrate. The gate conductor material is preferably polycrystalline silicon, or polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the "develop" stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
Conventional lithography used to pattern a gate conductor suffers many drawbacks. For example, selective exposure is highly dependent upon accurately placing light on the light-sensitive material. Furthermore, the light-sensitive material must consistently respond to the light with fine-line resolution. Any elevational disparity on which the polysilicon resides will result in slight changes in the point at which light impinges on the light-sensitive material. This results in a variation of the polymerized/non-polymerized boundary.
It would be advantageous to form a gate conductor without having to rely upon conventional patterning techniques. The impetus behind wanting to change gate formation methodology is principally driven from the smaller gate sizes of modern day integrated circuits. As gate lengths and widths become smaller to accommodate higher density circuits, it is necessary that the relatively small gate conductors be accurately produced with minimal misalignment or size variation. Any changes in the placement and geometry of a gate conductor can have negative performance effects on the ensuing MOS transistor.
To lower the resistivity of the polysilicon gate, and therefore increase the speed of the transistor it is desirable that the entire polysilicon layer forming the gate be substantially doped. During a typical transistor formation process the polysilicon gate is typically doped at the same time as the source/drain areas in order to make the process more efficient. This simultaneous implantation may cause difficulties since the implant depth of the gate is typically deeper than the desired implant depth of the source/drain. It is therefore desirable to devise a method which allows the implant depth of the gate to be conducted independently of the implantation of the source/drain.
It is further desirable to produce a gate conductor which is extremely small in channel length. The small gate conductor must be one which is formed outside of the normal lithography limitations. In order to accurately produce a small gate conductor, a process must be used which avoids the limitations of lithographic exposure, develop and etch cycles applied for defining conventional gate conductors upon a gate dielectric. In order for a transistor which employs a relatively small gate conductor to achieve commercial success, improvements must be undertaken not only to the lithography procedure but also to the LDD structure itself. As Leff decreases commensurate with gate conductor size, LDD implants must be carefully controlled so as not to encroach into the relatively short channel short channel while at the same time source/drain implants must be sufficiently concentrated to minimize HCE. Still further, the spacing of the source/drain implants must not be excessive, especially at the source-side of the channel, where parasitic resistance is most problematic.